Method for producing a semiconductor component with insulated semiconductor mesas

ABSTRACT

A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer.

RELATED APPLICATION

The present application is a continuation-in-part of previously filedU.S. Ser. No. 12/964,865 filed on Dec. 10, 2010, and herein incorporatedby reference in its entirety.

TECHNICAL FIELD

Embodiments of the present invention relate to a method for producing asemiconductor component with at least two semiconductor mesas which areinsulated from each other, and to a related semiconductor component.Further embodiments of the present invention relate to a method forproducing a semiconductor component with an electrically conductive viaextending through a semiconductor body, and to a semiconductor componentwith a via.

BACKGROUND

There are semiconductor components or devices which include at least apart of their device structure in the region of a first surface of asemiconductor body and which include a terminal for electricallycontacting the device structure at a second surface of the semiconductorbody. Such components further include an electrically conducting viawhich extends through the semiconductor body from the terminal at thesecond surface to the first surface.

The electrically conducting via is usually electrically insulated fromsurrounding regions of the semiconductor body. A via like this can beproduced by: forming a trench, depositing an electrically insulatingmaterial at the sidewalls of the trench, and filling the remainingtrench with an electrically conductive material.

There is a need to provide a method for producing a semiconductorcomponent with an electrically conductive via extending through asemiconductor body which is properly insulated from surrounding regionsof the semiconductor body.

Furthermore, insulating structures between different electronic circuitsare often desirable for semiconductor based integrated circuits (ICs).Accordingly, leakage current and unwanted mutual interference of thedifferent electronic circuits may be avoided or at least substantiallyreduced. Such devices may be manufactured using silicon on insulator(SOI) technology. However, SOI-technology is comparatively expensive.Furthermore, the material of the buried oxide (BOX) of the usedSOI-wafer is typically limited to silicon oxide (SiO₂) and sapphire.Accordingly, there is a need to provide a flexible and cost-efficientmethod for producing a semiconductor component with circuits which areinsulated from each other. This allows also flexible and cost-efficientproducing of semiconductor components such as TEDFETs having isolatedgate structures which extend along the whole drift zone and which cantake voltage during a blocking mode.

SUMMARY

According to an embodiment of a method for producing a semiconductorcomponent, the method includes: providing a semiconductor body with afirst surface and a second surface which is opposite to the firstsurface; forming an insulation trench from the first surface into thesemiconductor body; forming a first insulation layer at least on one ormore sidewalls of the insulation trench; removing semiconductor materialof the semiconductor body from the second surface to expose bottomportions of the first insulation layer and to form a back surface; anddepositing a second insulation layer on the back surface. The processesare carried out such that at least two semiconductor mesas are formedwhich are insulated from each other by the first insulation layer andthe second insulation layer.

According to an embodiment of a method for producing a semiconductorcomponent, the method includes: providing a semiconductor body with afirst surface and a second surface opposite to the first surface;etching an insulation trench from the first surface partially into thesemiconductor body; forming a first insulation layer on one or moresidewalls of the insulation trench; processing the second surface by atleast one of grinding, polishing and a CMP-process to expose the firstinsulation layer; and depositing on the processed second surface asecond insulation layer which extends to the first insulation layer.

According to an embodiment of a semiconductor component, thesemiconductor component includes a semiconductor body with a firstsurface and a back surface opposite to the first surface. At least oneinsulation trench having a first insulation layer extending from thefirst surface to the back surface is formed in the semiconductor body.The semiconductor component further includes a second insulation layerdeposited on the back surface of the semiconductor body. The secondinsulation layer includes at least one of a silicon oxide, aluminumnitride, diamond like-carbon, boron-silicate glass, a spin-on glass, anorganosilicate dielectric, a silicone, a polymerized imide, a paryleneor a polymerized benzocyclobutene, a synthetic material, and a curedresin. At least two semiconductor mesas are formed in the semiconductorbody. The at least two semiconductor mesas are laterally insulated fromeach other by the first insulation layer. At least one of the twosemiconductor mesas is completely insulated on the back surface by thesecond insulation layer.

According to an embodiment of a method for producing a semiconductorcomponent, the method includes: providing a semiconductor body with afirst surface and a second surface opposite the first surface; formingan insulation trench which extends into the semiconductor body from thefirst surface and which in a horizontal plane of the semiconductor bodydefines a via region of the semiconductor body; forming a firstinsulation layer on one or more sidewalls of the insulation trench;removing semiconductor material of the semiconductor body from thesecond surface to expose at least parts of the first insulation layer,to remove at least parts of the first insulation layer, or to leave atleast partially a semiconductor layer with a thickness of less than 1 μmbetween the first insulation layer and the second surface; forming afirst contact electrode on the via region in the region of the firstsurface; and forming a second contact electrode on the via region in theregion of the second surface.

According to an embodiment of a semiconductor component, the componentincludes: a semiconductor body with a first surface and a secondsurface; a first contact electrode in a region of the first surface; asecond contact electrode in a region of the second surface; asemiconductor via region extending between the first and second contactelectrodes; and an insulation layer separating the via region in ahorizontal direction of the semiconductor body from other regions of thesemiconductor body.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The components in the figures are not necessarily to scale, insteademphasis being placed upon illustrating the principles of the invention.Moreover, in the figures, like reference numerals designatecorresponding parts. In the drawings:

FIG. 1 which includes FIGS. 1A to 1H, illustrates vertical crosssections through a semiconductor body during a method according to afirst embodiment for producing a semiconductor component with asemiconductor via;

FIG. 2 illustrates a horizontal cross section through a semiconductorbody which includes a rectangular semiconductor via region;

FIG. 3 illustrates a horizontal cross section through a semiconductorbody which includes a circular semiconductor via region;

FIG. 4 illustrates a horizontal cross section through a semiconductorbody which includes a ring-shaped semiconductor via region;

FIG. 5 which includes FIGS. 5A to 5C, illustrates vertical crosssections through a semiconductor body during method steps of a methodaccording to a second embodiment;

FIG. 6 illustrates a vertical cross section through the semiconductorcomponent after process steps of a method according to a furtherembodiment;

FIG. 7 which includes FIGS. 7A to 7E illustrates vertical cross sectionsthrough a semiconductor body during method steps of a method which,besides a semiconductor via, produces a further via in the semiconductorvia region;

FIG. 8 illustrates a vertical cross section through a semiconductorcomponent produced in accordance with a modification of the methodaccording to FIG. 7;

FIG. 9 illustrates a vertical cross section through a transistorcomponent which includes a semiconductor via;

FIG. 10 illustrates a top view on one surface of a transistor componentaccording to a first embodiment;

FIG. 11 illustrates a top view on one surface of a transistor componentaccording to a second embodiment;

FIG. 12 illustrates a top view on one surface of a transistor componentaccording to a third embodiment;

FIG. 13 illustrates a top view on one surface of a semiconductor body inwhich two transistor components, each including a semiconductor via, areintegrated;

FIG. 14 illustrates a second embodiment of a semiconductor arrangementin which two transistor components, each including a semiconductor via,are integrated;

FIG. 15 illustrates a vertical cross-section through the componentaccording to FIG. 14 in a section plane C-C;

FIG. 16 illustrates a part of a vertical cross-section through asemiconductor body in which two transistor components are integrated;

FIG. 17 illustrates a horizontal cross-section through the arrangementof FIG. 16;

FIG. 18 illustrates a horizontal cross-section through a semiconductorbody according to a further embodiment in which two transistorcomponents are integrated;

FIGS. 19 to 27 illustrate vertical cross-sections through asemiconductor body during method steps of a method according to furtherembodiments;

FIGS. 28 to 29 illustrate vertical cross-sections through asemiconductor body during method steps of a method according to stillfurther embodiments;

FIG. 30 illustrates a vertical cross-section through a semiconductorbody of an integrated circuit with several semiconductor mesas, eachincluding a respective electronic circuit, according to an embodiment;

FIG. 31 illustrates a vertical cross-section through a semiconductorbody of a semiconductor device with several semiconductor mesas, eachincluding a respective electronic circuit, according to anotherembodiment;

FIG. 32 illustrates a vertical cross-section through a semiconductorbody of a semiconductor device with several semiconductor mesas, eachincluding a respective electronic circuit, according to yet anotherembodiment;

FIG. 33 illustrates a vertical cross-section through a semiconductorbody of a semiconductor device with two semiconductor mesas, eachincluding a respective electronic circuit, according to still anotherembodiment.

DETAILED DESCRIPTION

FIGS. 1A to 1H illustrate a first embodiment of a method for producing asemiconductor component with an electrically conductive via extendingthrough a semiconductor body. These figures show vertical cross-sectionsthrough a semiconductor body during or after particular method steps.

Referring to FIG. 1A, the semiconductor body 100 is provided. Thesemiconductor body 100 includes a first surface 101 and a second surface102 opposite the first surface 101. The vertical cross-sectionsillustrated in FIGS. 1A to 1H are cross-sections in a vertical sectionplane which is perpendicular to the first and second surfaces 101, 102.

The semiconductor body 100 can comprise a conventional semiconductormaterial, e.g. silicon (Si), silicon carbide (SiC), gallium arsenide(GaAs), gallium nitride (GaN), etc. The semiconductor body 100 is, inparticular, a monocrystalline semiconductor body.

According to a first embodiment, the semiconductor body 100 has ahomogeneous basic doping. Dependent on the specific type of thesemiconductor component which is to be implemented, the basic doping canbe an n-doping or a p-doping. According to a further embodiment, thesemiconductor body 100 includes two differently doped semiconductorlayers: a first semiconductor layer 110; and a second semiconductorlayer 120 on top of the first semiconductor layer 110. The firstsemiconductor layer 110 is, for example, a semiconductor substrate, andthe second semiconductor layer 120 is, for example, an epitaxial layergrown on the substrate 110. The two semiconductor layers 110, 120 canhave different doping concentrations and/or doping types. According toone embodiment, the first layer 110 has a higher doping concentrationthan the second layer 120. The doping concentration of the first layer110 is, for example, in the range of between 10¹⁸ cm⁻³ and 10²¹ cm⁻³while the doping concentration of the second layer 120 is, for example,in the range of between 10¹⁴ cm⁻³ and 10¹⁷ cm⁻³. The doping types of thedopings of the first and second layers 110, 120 can be identical or canbe complementary.

Referring to FIG. 1B, at least one insulation trench is formed whichextends into the semiconductor body 100 from the first surface 101. In ahorizontal plane of the semiconductor body 100, the at least oneinsulation trench 103 forms a closed loop or ring such that the at leastone insulation trench 103 encloses a region 11 of the semiconductor body100. The region 11 enclosed by the insulation trench 103 in thehorizontal direction of the semiconductor body 100 will be referred toas a via region in the following. In the horizontal plane, theinsulation trench 103 can be implemented in many different ways, i.e.with many different geometries. For illustration purposes, some exampleswill be explained with reference to embodiments illustrated in FIGS. 2to 4.

FIG. 2 shows a top view on the semiconductor body 100 after forming theinsulation trench 103. In the embodiment illustrated in FIG. 2, theinsulation trench 103 has a rectangular geometry. In this case, theinsulation trench 103 is implemented as a rectangular ring or loop in ahorizontal plane of the semiconductor body 100. Consequently, thesemiconductor via region 11 enclosed by the insulation trench 103 isrectangular in the horizontal plane.

In the embodiment illustrated in FIG. 3, the insulation trench 103 hasan ellipsoidal and, specifically, a circular geometry. Consequently, thesemiconductor via region 11 enclosed by the insulation trench 103 has anellipsoidal and, specifically, a circular geometry.

In the embodiments illustrated in FIGS. 2 and 3 the semiconductor viaregion 11 is defined by one insulation trench 103 which encloses thesemiconductor via region 11. However, an insulation trench 103 with arectangular geometry (see FIG. 2) or an ellipsoidal geometry (see FIG.3) are only exemplary embodiments. The insulation trench 103 can haveany other geometry, provided that the insulation trench 103 forms aclosed loop or ring enclosing the semiconductor via region 11.

According to a further embodiment which is illustrated in FIG. 4, thesemiconductor via region 11 is enclosed by two insulation trenches eachof which forms a closed loop: a first insulation trench 103 ₁, and asecond insulation trench 103 ₂ arranged within the loop defined by thefirst trench 103 ₁. The first and the second trenches 103 ₁, 103 ₂ arespaced apart from one another so that the semiconductor via region 11 isdisposed between the two trenches 103 ₁, 103 ₂. In the embodimentillustrated in FIG. 4, the first and second trenches 103 ₁, 103 ₂basically have a rectangular geometry. However, this is only an example.These two trenches 103 ₁, 103 ₂ may have any other closed-loop geometryother than a rectangular geometry as well.

In the embodiments illustrated in FIGS. 2, 3 and 4, the trench 103 (inthe horizontal plane) forms a closed loop which surrounds asemiconductor region, wherein the semiconductor region surrounded by thetrench forms the via region 11. The trench with the closed-loop geometryseparates the via region 11 in the horizontal direction from otherregions of the semiconductor body 100. However, it is not necessary forthe trench 103 to have a closed-loop geometry in order to define the viaregion 11. If, for example, the trench 103 is arranged close to an edgeof the semiconductor body 100 and terminates at the edge of thesemiconductor body 100, a closed-loop geometry is not required. This isillustrated in dashed lines in FIG. 2. In this Figure, reference numeral105 denotes an edge of the semiconductor body 100 at which thesemiconductor body 100 terminates.

A trench 103′ (illustrated in dashed lines) terminates at the edge 105and forms a closed loop with the edge so that the trench (together withthe edge 105 of the semiconductor body) defines the via region 11. Inthis connection usually a plurality of semiconductor bodies which arepart of a semiconductor wafer (not shown) are processed together, andthe wafer is separated to form the individual semiconductor bodies atthe end of such processing. Thus, when the trenches 103 or 103′,respectively, are formed, the wafer has not yet been separated. At thistime, lines (scribe lines) on the wafer define where the wafer is to beseparated and, therefore, define where the edges of the individualwafers will be. At this time of processing, the trench 103′ and thescribe line define the via region 11. The trench 103′ can also be formedwith a closed-loop geometry such that the trench 103′ extends into thescribe line. In this case, the closed loop defined by this trench 103′is “opened” when the wafer is cut into the individual semiconductorbodies (dies) by cutting along the scribe lines.

In the embodiments drawn in solid lines of FIGS. 2 and 3 the trenches103 define a silicon via 11 which is enclosed by the trench. Outside theclosed-loop defined by the trench active component region, like activeregions of a transistor can be arranged. In the embodiments of FIGS. 2and 3, the area of the semiconductor body 100 enclosed by the trench isselected such that a via with a suitable/desired ohmic resistance isobtained. According to a further embodiment, active component regionsare arranged in the semiconductor area enclosed by the trench 103 andthe via is defined by the trench and the edge 105 of the semiconductorbody 100. In this case, the via 11 (as shown in dotted lines in FIGS. 2and 3) is arranged between the edge 105 and the trench 103 and forms aclosed loop which encloses the trench 103, with the trench 103 forming aclosed loop that encloses the active regions, like e.g., a field oftransistor cells.

FIG. 1B represents a vertical cross-section through each of theembodiments illustrated in FIGS. 2, 3 and 4. In FIG. 1B, the referencesigns in parentheses represent the reference signs for the embodimentaccording to FIG. 4. In the following “at least one insulation trench”means either one trench 103 as illustrated in FIGS. 2 and 3, or twotrenches 103 ₁, 103 ₂ as illustrated in FIG. 4.

The at least one insulation trench 103, which extends in a verticaldirection of the semiconductor body 100, can be produced using anetching method. Etching methods for producing a vertical trench in asemiconductor body are commonly known, so that no further explanation isrequired in this regard. “To extend in a vertical direction” means thatthe at least one trench 103 generally extends in the vertical direction.However, the trench can also be inclined relative to the first surface101, so that an angle between sidewalls of the trench 103 and the firstsurface 101 can be different from 90°. The trench width can decrease orcan increase with depth. Both sidewalls can also be tilted toward thesame direction with the trench width being e.g. constant over the trenchdepth. The direction in which the trenches 103 are tilted can, forexample, vary over the wafer.

The at least one insulation trench 103 is produced such that it does notcompletely extend through the semiconductor body 100 to the secondsurface 102. A depth of the insulation trench 103 is, for example, inthe range of between 5 μm and 200 μm, in particular between 30 μm and 60μm, like about 50 μm. A width of the trench is, for example, in therange of between 200 nm and 20 μm.

Referring to FIG. 1C, a first insulation layer 21 is formed at least onthe sidewalls of the at least one insulation trench 103. In theembodiment illustrated in FIG. 1C, the first insulation layer 21 isformed on the sidewalls and on the bottom of the at least one insulationtrench 103. The first insulation layer 21 is, for example, an oxidelayer. The oxide layer can be produced by a thermal oxidation processand/or by a deposition process. The method, however, is not restrictedto the use of an oxide as the insulation layer 21. Any other type ofinsulation or dielectric material may be used as well, like a nitride,aluminum oxide (Al₂O₃) or a low-k-dielectric. According to oneembodiment, the first insulation layer 21 is a composite layer whichincludes two or more layers of an insulation material arranged one abovethe other.

Optionally, a doped semiconductor region 12 (illustrated in dashedlines) is produced in the semiconductor body 100 adjacent the insulationtrench 103. The doped semiconductor region 12 has a higher dopingconcentration than the basic doping of the semiconductor body 100 or,when the semiconductor body 100 includes a higher doped first layer 110and a lower doped second layer 120, has a doping concentration which isat least higher than the doping concentration of the lower dopedsemiconductor layer 120. The doped semiconductor region 12 is producedadjacent to the trench 103 at least in the via region 11, but can alsobe produced along the complete side walls and the bottom of theinsulation trench 103. Forming the higher doped region 12 includes, forexample: a deposition process, in which a doped glass or dopedpolysilicon is deposited, followed by a diffusion process; a gas phasedoping process; or an implantation and/or diffusion process in whichdopant atoms are implanted or diffused via the sidewalls (and optionallythe bottom) of the insulation trench 103 into the semiconductor body100.

In the embodiment illustrated in FIG. 1C the insulation layer 21 isproduced along the sidewalls and the bottom of the insulation trench 103such that a residual trench remains after the insulation layer 21 hasbeen produced. Referring to FIG. 1D, this residual trench is filled witha filling material 22. The filling material 22 is, for example, anelectrically conductive material, like a doped amorphous orpolycrystalline semiconductor material, such as polysilicon, a metal,silicide or carbon. According to a further embodiment, the fillingmaterial 22 is an insulating material, so that the insulation trench 21is completely filled with an insulation material. According to a furtherembodiment, which is illustrated in FIG. 6, the insulation layer 21 isproduced such that it completely fills the insulation trench 103, sothat there is no residual trench after the insulation layer 21 has beenproduced. In further embodiments a void may be enclosed in the trench103 if, e.g., the opening of the trench 103 is closed during depositionbefore the trench 103 has been completely filled.

The insulation and filling materials are typically also deposited on thefirst surface 101 (e.g. on the trench etch mask) and second surface 102,which is not shown in FIG. 1C. After trench filling, these layers can beremoved from the first and second surfaces 101, 102.

Referring to FIG. 1E, semiconductor material is removed from the secondsurface 102, so that a thickness—which corresponds to a verticaldimension of the semiconductor body 100—is reduced. For example, theremoval of the semiconductor material at the second surface 102 includesat least one of an etching process, a mechanical polishing process, or achemical-mechanical polishing (CMP) process. In FIG. 1E, referencecharacter 102′ denotes the second surface of the semiconductor body 100after the removal process. In the following, the second surface 102′ ofthe semiconductor body 100 is also referred to as back surface 102′. Itshould be mentioned that the semiconductor body is usually flipped orturned upside after having finished processing the first surface andbefore processing the second surface. However, for a betterunderstanding such flipping of the semiconductor body 100 is notillustrated.

Referring to the embodiment illustrated in FIG. 1E, the removal processcan be performed such that at the end of the removal process the firstinsulation layer 21 is uncovered at the second surface 102′. In theembodiment illustrated, the semiconductor material is removed down tobelow the bottom of the insulation trench 103, so that at the end of theremoval process the first insulation layer 21 at the bottom of theinsulation trench is uncovered at the second surfaces and protrudes fromthe second surface 102′. Thus, the second surface is not planarized inthis method.

In next method steps, a second insulation layer 31 is formed on thesecond surface 102′, with the second insulation layer 31 covering theuncovered region of the first insulation layer 21. Referring to FIGS. 1Fand 1G, producing the second insulation layer 31 includes, for example,forming an insulation layer 31′ which completely covers the secondsurface 102′ (see FIG. 1F) and forming a contact opening in theinsulation layer 31′, with the contact opening extending to the viaregion 11. The contact opening is produced such that remaining sections31 of the insulation layer 31′ form the second insulation layer 31 whichcovers the at least one insulation trench 103 with the first insulationlayer 21 at the second surface 102′. The second insulation layer 31 is,for example, an oxide layer or a nitride layer. The second layer 31includes, in particular, a material which does not require hightemperatures, like temperatures below 400° C., in the depositionprocess. Further suitable materials are, e.g., a spin-on glass or animide. Before removing semiconductor material at the second surface 102,the device structures at and below the first surface can be finished orfinally processed. This may include the deposition of metallizationlayers (not shown) on the first surface 101. Such metallization layers,however, cannot withstand high temperatures, like temperatures above400° C.

Forming the second insulation layer 31 is optional. The insulation layer21 at the bottom of the trenches can be sufficient to insulate the viaregion from surrounding semiconductor regions at the bottom of thetrench.

For forming the second insulation layer 31, which adjoins the firstinsulation layer 21, it is not necessary to uncover the first insulationlayer 21 in the removal process illustrated in FIG. 1E. According to analternative embodiment, the semiconductor material is not removed downto the first insulation layer 21, but a (thin) layer of semiconductormaterial having a thickness of less than 1 μm remains below the firstinsulation layer 21 in the region of the second surface 102′. This isillustrated in dotted lines in FIG. 1E. In this case, forming theinsulation layer 31′ (see FIG. 1F) involves a process which transformsthe semiconductor layer between the second surface 102′ and the firstinsulation layer 21 into an insulation layer. Such a process is, forexample, an oxidation process, like an anodic oxidation process, and/ora process in which oxygen is implanted into the semiconductor body 100via the second surface 102′.

After the process steps illustrated in FIGS. 1E to 1G, the semiconductorvia region 11 in a horizontal direction is completely enclosed by theinsulation trench with the first insulation layer 21 and by the secondinsulation layer 31. The semiconductor via region 21 forms anelectrically conductive connection between the first surface 101 and thesecond surface 102′ of the semiconductor body 100, and is electricallyinsulated from other regions of the semiconductor body 100.

Referring to FIG. 1H a first contact electrode 41 is formed on thesemiconductor via region 11 in the region of the first surface 101 and asecond contact electrode 42 is formed on the semiconductor via region 11in the region of the second surface 102′. To form the first and secondcontact electrodes 41, 42 in the region of the first and second surfaces101, 102, respectively, means that these electrodes 41, 42 can be formedon the respective surfaces 101, 102. However one or both of thesetrenches could also be formed in trenches, wherein each of thesetrenches extends from one of the surfaces 101, 102 into the via regionand includes one of the first and second electrodes 41, 42 contactingthe via region within the respective trench.

The first contact electrode 41 is, for example, a metal, a silicide, ora highly doped polycrystalline semiconductor material, such aspolysilicon. Optionally, a doped contact region 13 is formed in the viaregion 11 below the first surface 101 before forming the first contactelectrode 41. Such contact region can also be formed below the secondsurface 102′ before forming the second contact electrode 42. However,such contact region can be omitted, when the semiconductor body has ahigh basic doping, like in the region of the higher doped firstsemiconductor layer 110.

Although the method steps for producing the semiconductor via 11 withthe first and second contact electrodes 41, 42 have been illustrated ina certain order, the method is not restricted to perform these steps inany particular order. Rather, the order of method steps can be changed.For example, the first contact electrode 41 on the first surface 101 andthe optional contact region 13 can be produced before the removalprocess, or even before producing the insulation trench 103.

FIGS. 5A to 5C illustrate a further embodiment for producing asemiconductor via 11 in a semiconductor body 100. This method isbasically equivalent to the method illustrated in FIGS. 1A to 1H withthe difference that the second surface 102′ is planarized at the end ofor during the removal process so that the first insulation layer 21 inthe bottom region of the insulation trench 103 is removed. FIG. 5Aillustrates a vertical cross-section through the semiconductor body 100after these method steps. After these method steps the first insulationlayer 21 is present on opposite sidewalls of the insulation trench 103and a filling material 22 is uncovered at the second surface 102′.Referring to the explanation provided herein above, the filling material22 is optional. As such, the insulation trench 103 can be completelyfilled with the first insulation layer 21.

The method steps illustrated in FIGS. 5B and 5C for forming the secondinsulation layer 31 on the second surface 102′, and for forming thefirst and second contact electrodes 41, 42 correspond to the methodsteps illustrated in FIGS. 1F to 1H to which reference is made,respectively. The second insulation layer 31 covers the insulationtrench 103 at the second surface 102′ and leaves a contact opening abovethe semiconductor via region 11.

The method steps illustrated in FIGS. 4, 5A and 5B may also be describedas a method for producing a semiconductor component with severalsemiconductor mesas which are laterally insulated from each other by afirst insulation layer 21 arranged on one or more insulation trenches103 ₁, 103 ₂. The method includes: providing a semiconductor body 100with a first surface 101 and a second surface 102 opposite to the firstsurface 102; etching one or more insulation trenches 103 ₁, 103 ₂ fromthe first surface 101 partially into the semiconductor body 100; forminga first insulation layer 21 on one or more sidewalls of the insulationtrenches 103 ₁, 103 ₂; processing the second surface 102 by at least oneof grinding, polishing, a CMP-process, chemical etching and plasmaetching to expose the first insulation layer 21; and, depositing on theprocessed second surface 102′ a second insulation layer 31′ whichextends to the first insulation layer 21.

In the exemplary embodiment illustrated in FIG. 5B, three semiconductormesa regions are shown, which are insulated from each other by the firstinsulation layer 21 arranged on the sidewalls of the insulation trenchesand by the second insulation layer 31′ arranged on the back surface102′. Later, the second insulation layer 31′ may partially be removed toform a via region in the central semiconductor mesa as illustrated inFIG. 5C. In further embodiments, all or at least several semiconductormesa regions of the final semiconductor component remain completelyinsulated on the back surface 102′. In these embodiments, the remainingsections 31 of the insulation layer 31′ form the second insulation layer31 which forms together with the first insulation layer 21 an insulatingstructure for the mutually insulated semiconductor mesas. Typically, theinsulated semiconductor mesas include separated semiconductor structuresforming at least parts of different electronic circuits. Accordingly, anintegrated circuit with low cross-talk between the different electroniccircuits and/or low leakage current may be provided. Further examplesare explained below with regard to FIGS. 19 to 33. Such semiconductorcomponents may also be manufactured by SOI-technology, however at highercosts. This is mainly due to the costs of SOI-wafers which are typicallyabout four to ten times higher compared to similar wafers but without aburied oxide layer.

Referring to the explanation provided hereinabove, the first insulationtrench 103 can be filled completely with the first insulation layer 21,where the first insulation layer 21 may also be produced as a stack ofdifferent material layers and may contain voids. A verticalcross-section through the semiconductor body 100 having the insulationtrench 103 filled completely with the first insulation layer 21 isillustrated in FIG. 6. FIG. 6 shows a vertical cross section through thesemiconductor body 100 before removing semiconductor material from thesecond surface 102 and before producing the first and second contactelectrodes 41, 42.

The ohmic resistance of the semiconductor via region 11 between thefirst and second contact electrodes 41, 42 is, amongst others, dependenton the length of the via region 11, with the length corresponding to thevertical thickness of the semiconductor body 100, the area of thehorizontal cross-section of the semiconductor via region 11, and thedoping concentration of the via region 11. The ohmic resistance of thesemiconductor via region 11 can be reduced by providing the higher dopedregions 12 along the sidewalls of the insulation trench 103.

According to a further embodiment, the ohmic resistance of thesemiconductor via region 11 can be reduced by additionally providing acontact trench filled with an electrically conductive material withinthe semiconductor via region 11. Such contact trench can be providedoptionally or additionally to the higher doped semiconductor region 12.An embodiment of a method for producing a semiconductor via region 11with a contact trench is explained next with reference to FIGS. 7A to7E. These figures each show a vertical cross section through thesemiconductor body 100 during particular steps of the method. Althoughthese method steps are illustrated in a certain order in the figures,this order can be changed.

Referring to FIG. 7A this method involves, besides forming theinsulation trench 103 and filling the insulation trench 103, forming acontact trench 104 which extends from the first surface 101 into thesemiconductor body, and filling the contact trench 104 with anelectrically conductive material 23. The electrically conductivematerial 23 is, for example, a doped amorphous or polycrystallinesemiconductor material, such as polysilicon, a metal, a silicide, orcarbon. According to one embodiment, the contact trench 104 is filledwith a layer stack which includes at least two different electricallyconductive layers. Optionally a diffusion barrier or a third insulationlayer 24 is formed along the sidewalls of the contact trench 104 beforefilling the trench 104 with the electrically conductive material 23. Theelectrically conductive material 23 forms a conductive via within thesemiconductor via region 11. The contact trench 104 can be produced suchthat it is arranged distant to the insulation trench 103. The positionof the contact trench 104 within the semiconductor via region 11 isillustrated in dashed lines in the embodiments illustrated in FIGS. 2, 3and 4.

The insulation trenches can include the first insulation layer 21 and anelectrically conductive filling material 22, as illustrated in FIG. 7A.Alternatively, the insulation trench 103 can be completely filled withthe first insulation layer 21 as illustrated in FIG. 6.

The remaining method steps illustrated in FIGS. 7B to 7E correspond tothe method steps illustrated in FIGS. 1E to 1H, respectively. Thesemethod steps include partially removing the semiconductor body 100 atthe second surface 102 (see FIG. 7B), forming the second insulationlayer 31 adjacent to the first insulation layer 21 (see FIGS. 7C and7D). The contact opening in the insulation layer 31′ is formed such thatthe contact opening uncovers the contact via 23 at the second surface102′. Referring to FIG. 7E, the first and second contact electrodes 41,42 are formed on the contact via 23 and the semiconductor via 11 on thefirst surface 101 and on the second surface 102, respectively.

Forming the insulation trench 103 and the contact trench 104 may includecommon method steps. According to one embodiment these trenches 103, 104are etched by the same etching process. Further, when the fillingmaterial 22 of the insulation trenches 103 is an electrically conductivematerial, the filling material 22 in the insulation trenches 103 and theelectrically conductive material 23 in the contact trench 104 can beproduced by the same method steps.

In the method illustrated in FIGS. 7A to 7E, the first insulation layer21 at the bottom of the insulation trench 103 is preserved during theprocess of partially removing the semiconductor body 100 at the secondsurface 102. This is in correspondence with the method illustrated inFIGS. 1A to 1H.

According to one embodiment, the contact trench 104 is produced toextend deeper into the semiconductor body 100 from the first surface 101than the insulation trenches 103. A deeper contact trench 104 can beproduced using the same process that produces the insulation trenches103 when the contact trench 104 is wider than the insulation trenches103. After the contact trench 104 is filled with the electricallyconductive material 23, and when the semiconductor material is removedfrom the second surface 102, the contact electrode 23 in the (deeper)contact trench 104 is uncovered before the insulation trenches 103 arereached. This allows to uncover the contact electrode 23 at the secondsurface 102′ without removing the insulation layer 21 at the bottom ofthe insulation trenches 103.

However, similarly to the method illustrated in FIGS. 5A to 5C, thefirst insulation layer 21 can be partially removed at the bottom of theinsulation trench 103 during the removal process, so that the fillingmaterial 22 is uncovered at the bottom of the trench 103, if there is afilling material 22 besides the first insulation layer 22. Asemiconductor component produced in accordance with this modification isillustrated in FIG. 8.

The semiconductor via region 11 and the optional contact via 23 can beused to connect any type of component region or device structure whichis arranged in the region of the first surface 101 of the semiconductorbody 100 with the second contact electrode 42 at the second surface102′. FIG. 9 illustrates a vertical cross-section through a transistor,specifically a vertical MOS transistor. The MOS transistor isimplemented in a semiconductor body 100 which includes a highly dopedfirst semiconductor layer 110 and a lower doped second semiconductorlayer 120. The MOS transistor includes a drain region 54 which isimplemented by the first semiconductor layer 110 and which is contactedby a drain electrode 56 arranged on the second surface 102′. The drainelectrode 56 forms a drain terminal D of the MOS transistor. The MOStransistor further includes a drift region 53 adjacent the drain region54. The drift region 53 is formed by those sections of the firstsemiconductor layer 120 which have a basic doping of the second layer120. The transistor further includes at least one transistor cell with asource region 51, a body region 52 arranged between the source region 52and the drift region 53, and a gate electrode 61 arranged adjacent thebody region 52 and dielectrically insulated from the body region 52 by agate dielectric 62.

In FIG. 9, several transistor cells with a source region 51 and a bodyregion 52 are illustrated. In the embodiment illustrated in FIG. 9, thegate electrode 61 is implemented as a trench-gate-electrode, which is agate electrode arranged in a trench and extending from the first surface101 into the semiconductor body 100. Implementing the gate electrode 61as a trench-electrode, however, is only an example. The gate electrode61 could also be implemented as a planar electrode, which is anelectrode arranged above the first surface 101 of the semiconductor body100. In FIG. 9, different sections of the gate electrode 61 are shown.These sections of the gate electrode 61 are electrically connected witheach other in a manner not illustrated. For example, the gate electrode61 has a grid-shaped geometry in the horizontal plane. Or, theindividual sections 61 illustrated in FIG. 9 in a directionperpendicular to the section plane illustrated in FIG. 9 arelongitudinal electrode sections. These longitudinal gate electrodesections can be electrically connected with each other by a connectionarranged in a trench (not shown) which extends perpendicular to the gateelectrode sections 61.

The gate electrode 61 is electrically connected to the first contactelectrode 41, with the first contact electrode 41 dielectricallyinsulated by an insulation layer 71 from regions of the semiconductorbody 100 which are outside the via region 11, and optionally from thetrench filling material 22. Via the contact electrode 41 and thesemiconductor via 11 the gate electrode 61 is electrically connected tothe second contact electrode 42 arranged on the second surface 102′. Inthe following, the first contact electrode 41 is also referred to as awiring. In the exemplary embodiment, only one wiring 41 is formed on thefirst surface 101.

Thus, a gate terminal G of the MOS-transistor is formed by the secondcontact electrode 42 arranged on the second surface 102′ of thesemiconductor body. The individual source regions 51 and the bodyregions 52 are electrically connected to a source electrode 55 which isdielectrically insulated from the gate electrode 61. The sourceelectrode 55 is arranged on top of the first surface 101 of thesemiconductor body. This vertical MOS transistor has its sourceelectrode 55 above the first surface 101, and has its gate electrode 42and its drain electrode 56 arranged on the second surface 102′ of thesemiconductor body.

The source electrode 55 is electrically connected to an electrode layer57, like a metallization layer, which is arranged above the sourceelectrode 55 and the gate contact electrode 41 and which isdielectrically insulated from the gate contact electrode 41 by a furtherdielectric layer 72. The electrode layer 57 forms an outer sourceelectrode which, by virtue of its planar surface, can be mounted to aleadframe (not shown).

Alternatively a single layer metallization with a predominantly flatsurface can be used and the gate contact electrode 41 can be made from adifferent material like highly doped polysilicon.

In this connection it should be mentioned that before producing the gateelectrode 42 and the drain electrode 56 on the second surface 102′contact implantations can be made, which are implantations which serveto reduce the ohmic resistance between the via region 11 and the gateelectrode 42 and between the drain region 54 and the drain electrode 56.

In the embodiment illustrated in FIG. 9, the drain region 54 is formedby a highly doped semiconductor layer 110, like a substrate, on which alower doped layer 120, like an epitaxial layer, in which the driftregion 53 is implemented is arranged. According to a further embodiment,the semiconductor body 100 has a basic doping which corresponds to thedoping of the drift region 53. In this case, the drain region 54—and anoptional field stop region in an IGBT—are formed by an implantationand/or diffusion and/or annealing process before producing the drainelectrode 56. In this case, the vertical thickness of the semiconductorbody 100 defines the length of the drift region 53.

Referring to FIG. 9, a passivation layer 73 can be formed on the secondsurface 102′ or on the second insulation layer 31 (if a secondinsulation layer has been produced). The passivation layer 73 hascontact openings above the gate electrode 41 and the drain electrode 56.As such, the gate electrode 42 and the drain electrode can be producedwith the same method steps or can be part of one structuredmetallization layer.

The MOS transistor can be implemented as an n-type transistor or ap-type transistor. In an n-type transistor the source region 51 and thedrift region 53 are n-doped, while the body region 52 region is p-doped.In a p-type transistor the source region 51 and the drift region 53 arep-doped, while the body region 52 is n-doped. The MOS-transistor can beimplemented as a MOSFET or as an IGBT. In a MOSFET the drain region 54has the same doping type as the source region 51, and in an IGBT thedrain region 54 (which is also referred to as collector region) has adoping type which is complementary to the doping type of the sourceregion 51.

The second contact electrode or gate electrode 42 and the drainelectrode 56 can be arranged in many different ways on the secondsurface 102′ of the semiconductor body 100. Three different embodimentsare explained next with reference to FIGS. 10 to 12 each of which showsa horizontal cross-section through the second contact electrode 42 andthe drain electrode 56 in a horizontal section plane B-B illustrated inFIG. 9.

In the embodiment illustrated in FIG. 10, the drain electrode 56 and thegate electrode 52 are arranged next to each other, with the drain region56 having a cut-out region in which the gate electrode 42 is arranged.The drain electrode 56 and the gate electrode 42 are electricallyinsulated from one another by the second insulation layer 31 and/orinsulation layer 21.

In the embodiment illustrated in FIG. 11, the gate electrode 42 issurrounded by the drain electrode 56, with the gate electrode 42 and thedrain electrode 56 being electrically insulated from one another by thesecond insulation layer 31.

In the embodiment illustrated in FIG. 12, the gate electrode 42surrounds the drain electrode 56, with these two electrodes 42, 56 beingelectrically insulated from one another by the second insulation layer31 and/or insulation layer 21. In the embodiment according to FIG. 12the gate electrode 42, like the semiconductor via region 11, has aring-shaped geometry.

In other embodiments gate electrode 42 and via region 11 have differentshapes. The drain electrode 56 can overlap with the via region 11. Thisrequires however an insulation region between the gate electrode 42 andthe drain regions as well as between the drain electrode 56 and the viaregion 11.

Two MOS-transistors can be implemented in a single semiconductor body.FIGS. 13 and 14 show horizontal cross-sections through gate electrodesand drain electrodes of two MOS-transistors implemented in onesemiconductor body 100. In the embodiment illustrated in FIG. 13, afirst gate electrode 42 ₁ and a first drain electrode 56 ₁ of a firstMOS transistor are arranged next to each other and electricallyinsulated from one another by a second insulation layer 31 ₁. Further, asecond gate electrode 42 ₂ and a second drain electrode 56 ₂ of a secondMOS transistor are arranged next to each other and electricallyinsulated from one another by a second insulation layer 31 ₂. Inaddition one or more insulation trenches 103 can be provided between thedrain electrodes 56 ₁ and 56 ₂ or surrounding one or bothMOS-transistors to laterally insulate the drain and source potentialsfrom one another. The source regions can be connected to a common sourceelectrode or to electrically insulated source electrodes. Thus commonsource or common drain devices can be realized.

In the embodiment illustrated in FIG. 14, a first drain electrode 56 ₁is surrounded by a first gate electrode 42 ₁ and a second drainelectrode 56 ₂ surrounded by a second gate electrode 42 ₂, with thefirst and second gate electrodes 42 ₁, 42 ₂ being arranged distant fromone another in a horizontal direction of the semiconductor body.

FIG. 15 illustrates a vertical cross-section through the semiconductorbody 100 of FIG. 14 in a vertical section plane C-C. In this verticalcross-section section of the first and second gate electrodes 42 ₁, 42₂, of the corresponding first contact electrodes 42 ₁, 42 ₂, and thesemiconductor via regions 11 ₁, 11 ₂ are shown. Reference numerals 21 ₁and 21 ₂ denote respective first insulation layers. In the embodimentillustrated in FIG. 15 the insulation trenches are completely filledwith the first insulation layers 21 ₁, 21 ₂. However, this is only anexample. These insulation trenches could also be implemented to befilled with the first insulation layer and a filling material e.g. asshown in FIG. 1D.

The first and second semiconductor vias 11 ₁, 11 ₂ illustrated in FIG.15 are each produced (defined) by two insulation trenches 103 ₁₁, 103 ₁₂and 103 ₂₁, 103 ₂₂, respectively. In a horizontal direction the firstand second vias 11 ₁, 11 ₂ are separated from one another by two firstinsulation layers 21 ₁, 21 ₂ and a semiconductor region 13 arrangedbetween the two first insulation layers 21 ₁, 21 ₂.

FIG. 16 illustrates a further embodiment, in which the two semiconductorvia regions 11 ₁, 11 ₂ are only separated by one insulation trench witha first insulation layer 21 ₁₂. In this embodiment, the insulationtrench between the semiconductor vias 11 ₁, 11 ₂ is completely filledwith the insulation layer 21 ₁₂. However, this is only an example, thisinsulation trench could also be filled with the first insulation layer21 ₁₂ and an additional filling material e.g. as shown in FIG. 1D. FIG.17 illustrates a horizontal cross-section through the arrangementaccording to FIG. 16 in a horizontal section plane D-D.

FIG. 18 illustrates a further embodiment of a transistor arrangementwith two MOS-transistors integrated in a semiconductor body 100. FIG. 18illustrates a horizontal cross-section in a horizontal section planethrough the gate electrode and the drain electrode. In this embodimentbetween the semiconductor via regions 11 ₁ and 11 ₂ a semiconductorregion 13 is arranged, and between the semiconductor via regions 11 ₁,11 ₂ and the drain electrodes or drain regions 54 ₁, 54 ₂ additionalsemiconductor regions 14 ₁, 14 ₂ are arranged, with the additionalsemiconductor regions 14 ₁, 14 ₂ being insulated from the drain regions54 ₁, 54 ₂ by additional insulation trenches formed in correspondencewith the insulation trenches 103 ₁, 103 ₂. These additional insulationtrenches are filled with additional insulation layers 24 ₁, 24 ₂.Optionally, these additional insulation trenches are filled with theadditional insulation layers 24 ₁, 24 ₂ and a filling material, like theinsulation trenches 103 illustrated in FIG. 1D. In this embodiment, theadditional semiconductor regions 14 ₁, 14 ₂ separate the via regions 11₁, 11 ₂ from the drain regions.

According to one embodiment, the semiconductor region 13 and thesemiconductor regions 14 are connected to terminals for a definedelectrical potential, such as ground or source potential, wherein sourcepotential is the electrical potential of the source electrode 55.Thereby the capacitive coupling between the gates of the two transistorsor between gate and drain of one transistor is significantly reduced.

With regard to FIGS. 19 to 27 further embodiments of a method forproducing a semiconductor component 1000 with at least laterallyinsulated semiconductor mesas is illustrated. These figures showvertical cross-sections through a semiconductor body 100 during or afterparticular method steps.

Referring to FIG. 19, a semiconductor body 100 is provided. Thesemiconductor body 100 includes a first surface 101 and a second surface102 which is opposite to the first surface 101.

According to an embodiment, the semiconductor body 100 includes twodifferently doped semiconductor layers: a first semiconductor layer 110;and a second semiconductor layer 120 on top of the first semiconductorlayer 110. The first semiconductor layer 110 is, for example, asemiconductor substrate, and the second semiconductor layer 120 is, forexample, formed by the illustrated one or by more epitaxial layers 2grown on the substrate 110 and over each other, respectively. The twosemiconductor layers 110, 120 can have different doping concentrationsand/or doping types as explained above with regard to FIG. 1A. Thedoping types of the dopings of the first and second layers 110, 120 canbe identical or can be complementary so that a substantially horizontalpn-junction 14 is formed between the first layer 110 and the secondlayer 120. Alternatively, the semiconductor body 100 may have ahomogeneous basic doping. In the exemplary embodiment, the firstsemiconductor layer 110 is higher doped than the second semiconductorlayer 120.

Referring to FIG. 20, at least one insulation trench 103 ₁, 103 ₂ isformed which extends into the semiconductor body 100 from the firstsurface 101. Typically, insulation trenches 103 ₁, 103 ₂ are etched intothe semiconductor body 100, for example using a Bosch process.

In a horizontal plane, the at least one insulation trench 103 ₁, 103 ₂can be implemented in many different ways, i.e. with many differentgeometries. The illustrated insulation trenches 103 ₁, 103 ₂ may besubstantially ring-shaped as explained above with reference toembodiments illustrated in FIGS. 2 to 4. Accordingly, two insulationtrenches 103 ₁, 103 ₂ which are separated from each other in verticalcross-sections may correspond to portions of one connected insulationtrench 103 ₁, 103 ₂.

Note that the shown vertical cross-section typically corresponds only toa section through the semiconductor body 100. The semiconductorcomponent 1000 may include a plurality of insulation trenches 103 ₁, 103₂ defining in the horizontal plane an array of semiconductor mesaregions 100 a, 100 b, and 100 c in the semiconductor body 100. The arraymay, at least in a horizontal area, be regular. In other embodiments,the semiconductor mesa regions 100 a, 100 b, 100 c are, in thehorizontal plane, differently shaped and/or sized depending on thesemiconductor structures to be formed therein.

As illustrated in FIG. 20, the insulation trenches 103 ₁, 103 ₂typically extend completely through the epitaxial layer 120 andpartially into the substrate 110. Accordingly, the epitaxial layer 120is, at least in the shown vertical cross-section, subdivided indifferent portions 2 a, 2 b, and 2 c. When the shown insulation trenches103 ₁, 103 ₂ correspond to portions of a single insulation trench 103 ₁,103 ₂, the portions 2 a, 2 c of epitaxial layer 120 are typically alsoconnected.

In the exemplary embodiment, each semiconductor mesa regions 100 a, 100b, 100 c includes a portion 14 a, 14 b, 14 c, of the pn-junction 14. Thepn-junctions 14 a, 14 b, 14 c may, for example, form a part of arespective diode structure or a transistor structures in the finalsemiconductor component 1000.

In particular insulation trenches 103 ₁, 103 ₂ of high aspect ratio maybe formed differently. In a first step a wide trench that extends, inhorizontal direction of the shown vertical cross-section, substantiallybetween the outer side walls of the shown insulation trenches 103 ₁, 103₂ may be etched using an etching mask, for example a photoresist, asilicon oxide or silicon nitride hard mask. Thereafter, an oxide layermay be formed on the side walls of the wide trench. This is typicallydone by thermal oxidation and anisotropic etching to remove the thermaloxide formed at the bottom wall of the wide trench as well as at thefirst surface 101 while leaving a part of the hard mask on the firstsurface 101. The width of the oxide layer and the thermal oxide on theside wall of the wide trench substantially matches the desired width orabout half of the desired width of the shown insulation trenches 103 ₁,103 ₂. Thereafter, the wide trench is filled with semiconductor materialusing selective epitaxy. Any semiconductor material protruding out ofthe first surface 101 is typically removed, for example by aCMP-process. The etching mask and/or the oxide layer may now be removed.This process sequence results also in a structure as shown in FIG. 20.

As explained above with regard to FIGS. 1E and 5A, the semiconductorbody 100 is later to be thinned at the second surface 102 at least tothe insulation trenches 103 ₁, 103 ₂ to form separated semiconductormesa regions 100 a, 100 b, 100 c. Accordingly, the insulation trenches103 ₁, 103 ₂ are typically etched to a vertical depth d₂ which is largerby about 5% to about 30%, more typically by about 15% to about 25% thanthe final vertical thickness of the semiconductor body 100. The finalvertical thickness of semiconductor body 100 may be smaller than 100 μmor even smaller than 50 μm. Wafer of such vertical extension aretypically to be supported during processing. Therefore, the verticalextension d₁ of semiconductor body 100 prior to thinning is typicallylarger, for example larger than about 250 μm. The vertical extension d₁of semiconductor body 100 prior to thinning may, for example, be about700 μm.

Thereafter, a first insulation layer 21 is formed at least on onesidewall of the insulation trenches 103 ₁, 103 ₂, typically on allsidewalls of the insulation trenches 103 ₁, 103 ₂. The resultingsemiconductor component 1000 is illustrated in FIG. 21.

In the exemplary embodiment, the insulation trench 103 ₁ is completelyfilled with the first insulation layer 21 while the first insulationlayer 21 only covers the sidewalls of insulation trench 103 ₂. This is,however, only an example. Typically, the insulation trenches 103 ₁, 103₂ of semiconductor component 1000 are formed in common processes toreduce processing complexity. Accordingly, the insulation trenches 103₁, 103 ₂ of the semiconductor component 1000 may have the samestructure.

The inner part of in insulation trench 103 ₂, i.e. the residual trench,is filled with a filling material 22 which may be an insulating materialor an electrically conductive material as explained above, for examplewith respect to FIG. 1C, such as an amorphous or polycrystallinesemiconductor material, for example polysilicon, a metal like copper orwolfram, a silicide, or carbon. Filling the inner part of insulationtrench 103 ₂ with a material that is different to the material of thefirst insulation layer 21 may reduce mechanical stress. Thus, the riskof breaking semiconductor body 100 during further processing may bereduced.

The first insulation layer 21 may be formed by thermal oxidation, and/orby deposition and a subsequent planarization process. The fillingmaterial 22 is typically formed by deposition and a subsequentplanarization process. This allows substantially cavity-free filling ofthe insulation trench 103 ₂. Accordingly, the risk of breakingsemiconductor body 100 during further processing may be further reduced.

As illustrated in FIG. 22, the insulation trenches 103 ₁, 103 ₂ may betapered. Accordingly, a horizontal extension of the insulation trenches103 ₁, 103 ₂ may be smaller in a lower portion of the insulationtrenches 103 ₁, 103 ₂ compared to a respective upper portion which iscloser to the first surface 101. This may be achieved by aBosch-process.

Depending on the functions of the semiconductor component 1000, severalsemiconductor regions or semiconductor zones such as source or emitterregions may additionally be formed from the first surface 101 in theportions 2 a, 2 b, and 2 c of epitaxial layer 120. In or on eachsemiconductor mesa region 100 a, 100 b, and 100 c an active and/orpassive electric component such as a resistor, a capacitor, a diode anda transistor or even a complete circuitry may be formed. For example aMOSFET-structure may be formed in at least one of the semiconductormesas 100 a, 100 b, and 100 c. Beside additional semiconductor zones, aninsulated gate electrode structure on the first surface 101 or in atrench extending form the first surface 101 into respectivesemiconductor mesa 100 a, 100 b, 100 c may be formed. For sake ofclarity, these structures are not illustrated in FIG. 22.

Thereafter, an interlayer dielectric 8, for example a phosphosilicateglass (PSG) layer, with conductive through contacts 10 a, 10 b, 10 c incontact with at least some of the semiconductor zones are formed on thefirst surface 101. The resulting semiconductor component 1000 isillustrated in FIG. 23.

Furthermore, a wiring (not shown in FIG. 23) between at least two of thesemiconductor mesas 100 a, 100 b, 100 c may be formed on the firstsurface 101.

Thereafter, at least one metallization or terminal 55 may be formed onthe first surface 101 to contact the electric components and circuits,respectively, formed in the semiconductor mesas 100 a, 100 b and 100 c.The resulting semiconductor component 1000 is illustrated in FIG. 24.

For sake of clarity, only one metallization 55, forming for example asource metallization for a transistor structure and/or an emittermetallization for an IGBT-structure and/or a diode structure, isillustrated in FIG. 24. Depending on function of the final semiconductorcomponent 1000, several metallizations may be arranged on the firstsurface 101. For example, a drain metallization and a gate metallizationmay additionally be arranged on the first surface 101. In otherembodiments, the drain metallization and/or a gate metallization arelater arranged opposite to the source metallization 55. In theseembodiments, a via region through the semiconductor body mayadditionally be provided for contacting gate electrodes formed next tothe first surface 101 to the gate metallization formed opposite to thefirst surface 101, as explained above with regard to FIGS. 1 to 18. Inyet other embodiments additional via regions through the semiconductorbody may be provided to connect other electrodes to additionalmetallizations on a back surface 102′ to be formed. Now, processing ofsemiconductor component 1000 from the first surface 101 is typicallyfinished.

For thinning and further backside processing, the semiconductor body 100is thereafter typically mounted with the first surface 101 on a carriersystem 60, for example glued to a glass substrate or glass wafer 60. Ifthe final thickness of the semiconductor body 100 is larger than about200 μm, the semiconductor body 100 may also be mounted on a foil or evenfurther processed without any carrier system.

Thereafter, semiconductor material of the semiconductor body 100 isremoved from the second surface 102 to expose bottom portions of thefirst insulation layer 21 and the insulation trenches 103 ₁, 103 ₂,respectively, and to form a back surface 102′. Accordingly,semiconductor mesas 100 a, 100 b, 100 c are formed which are, at leastin the vertical cross-section, separated from each other and laterallyinsulated from each other by the insulation trenches 103 ₁, 103 ₂, andthe first insulation layer 21, respectively. The resulting semiconductorcomponent 1000 is illustrated in FIG. 25. In the exemplary embodiment,each of the semiconductor mesas 100 a, 100 b, 100 c include a portion 2a, 2 b and 2 c, respectively, of epitaxial layer 120 and a respectiveadjoining portion 1 a, 1 b, 1 c of the substrate 110.

By removing semiconductor material of the semiconductor body, thesemiconductor body 100 is thinned to a final vertical thickness d₃between the first surface 101 and the back surface 102′. A lowermostportion of the insulation trenches 103 ₁, 103 ₂ may be removed duringthis process. For example, the final vertical thickness d₃ may be about5% to 30%, more typically about 15% to about 25% smaller than thevertical etching depth d₂ of the insulation trenches 103 ₁, 103 ₂.

According to an embodiment, the semiconductor body 100 is thinned to avertical thickness d₃ between the first surface 101 and the back surface102′ of less than about 50 μm, for example to about 40 μm, by removingsemiconductor material of the semiconductor body 100. When thesemiconductor body 100 is attached to a sufficiently stable carriersystem 60 such as a glass wafer, semiconductor components 1000 with verythin semiconductor body 100 can be fabricated. This is particularlyinteresting for low voltage applications.

Removing semiconductor material of semiconductor body 100 is typicallyachieved by a combination of mechanical thinning, for example grindingor polishing, a CMP-process, with chemical and/or plasma etching toachieve a sufficiently low surface roughness of back surface 102′. Forexample, a grinding-process is used to remove a larger portion of thesemiconductor material. Thereafter, etching may be used to removefurther semiconductor material of semiconductor body 100, for example afew microns, until the desired final vertical thickness d₃ ofsemiconductor body 100 is reached. The semiconductor material may beetched selectively to the first insulation layer 21 and/or the fillingmaterial 22. In this embodiment, the first insulation layer 21 and/orthe filling material 22 may slightly protrude out of the back surface102′.

According to an embodiment, removing semiconductor material ofsemiconductor body 100 is carried out such that the back surface 102′ issubstantially scratch-free. For example, the surface roughness of backsurface 102′ is typically below 50 nm, more typically below 10 nm, andeven more typically below 1 nm. Accordingly, later depositions onto backsurface 102′ are facilitated.

According to still another embodiment, the removing semiconductormaterial of semiconductor body 100 is carried out such that the firstinsulation layer 21 and/or the filling material 22 are not exposed. Inthis embodiment a thin layer of semiconductor material covers the firstinsulation layer 21 and/or the filling material 22 after removingsemiconductor material of semiconductor body 100. The thin layer may becompletely oxidized in a later step.

Referring to FIG. 26, a second insulation layer 31′ is deposited on theback surface 102′ such that the second insulation layer 31′ extends toand adjoins, respectively, the first insulation layer 21. Accordingly,semiconductor mesas 100 a, 100 b, 100 c are formed which are insulatedfrom each other by the first insulation layer 21 and the secondinsulation layer 31′.

Typically, the second insulation layer 31′ is mask-less deposited on theback surface 102′. Thus, the semiconductor mesas 100 a, 100 b, 100 c arecompletely insulated on the back surface 102′ by the second insulationlayer 31′. In the exemplary embodiment, at least the centralsemiconductor mesas 100 b is completely insulated on the sidewalls andon the back-surface 102′ by an insulating structure formed by firstinsulation layer 21 on the sidewalls of the insulation trenches 103 ₁,103 ₂ and by the second insulation layer 31′. This applies also toembodiments in which the first insulation layer 21 and/or the fillingmaterial 22 slightly protrude out of the back surface 102′ afterremoving semiconductor material of semiconductor body 100. In theseembodiments, the second insulation layer 31′ is also formed on and indirect contact with the first insulation layer 21 and the fillingmaterial 22. In embodiments in which a thin layer of semiconductormaterial covers the first insulation layer 21 and the optional fillingmaterial 22 after removing semiconductor material of semiconductor body100, the second insulation layer 31′ is typically formed by anodicoxidation of the semiconductor material so that the second insulationlayer 31′ adjoins the first insulation layer 21 and the optional fillingmaterial 22.

The second insulation layer 31′ may completely cover the back surface102′ in the finally produced semiconductor component as secondinsulation layer 31. Alternatively, the deposited second insulationlayer 31′ may later partly be recessed so that remaining sections 31 ofthe insulation layer 31′ form the second insulation layer 31 in thefinally produced semiconductor component. In both cases at least one ofthe semiconductor mesas 100 a, 100 b, 100 c, for example the centralsemiconductor mesas 100 b is at the back surface 102′ completely coveredby the second insulation layer 31 which adjoins the first insulatinglayer 21. Accordingly, the semiconductor structures formed insemiconductor mesa 100 b are insulated from the neighboringsemiconductor mesas 100 a, 100 c. This at least reduces leakage currentand unwanted cross-talk between the semiconductor mesas 100 a, 100 b,and 100 c. The processes explained with regard to FIGS. 19 to 26 maytherefore be used to manufacture integrated circuits in which differentfunctions are realized in insulated semiconductor mesas 100 a, 100 b,100 c or insulated semiconductor wells 100 a, 100 b, 100 c.

Thereafter, a stabilizing layer 56′, for example a metal layer, may bedeposited on the second insulation layer 31. The resulting semiconductorcomponent 1000 is illustrated in FIG. 27.

In the exemplary embodiment, the semiconductor structures formed insemiconductor mesa 100 b are insulated from the neighboringsemiconductor mesas 100 a, 100 c by an insulating structure formed byfirst insulation layer 21 on the sidewalls of the insulation trenches103 ₁, 103 ₂ and by the second insulation layer 31. Accordingly, leakagecurrent and unwanted cross-talk between the semiconductor mesas 100 a,100 b, and 100 c is at least reduced.

The semiconductor component 1000 may now be removed from the carriersystem 60. Typically, a plurality of semiconductor component 1000 isformed in parallel on a common wafer, which may be cut into individualsemiconductor bodies (chips) prior to or after removing the common waferfrom the carrier system 60.

A similar semiconductor component as illustrated in FIGS. 26 and 27 mayalso by fabricated using SOI-technology. For example, deep verticaltrenches may be etched to a buried oxide layer of a SOI-wafer and filledwith a dielectric material. Accordingly, insulated wells may also beformed. However, this manufacturing method is more expensive due to themuch higher price of SOI-wafers compared to normal wafers.

Furthermore, not only silicon oxide and sapphire used in SOI-technologymay be used as material of the second insulation layer 31 in the methodsexplained herein. Depending on application and semiconductor material ofthe semiconductor body, the material of the second insulation layer 31may be chosen according to mechanical and/or thermal criterions. Forexample, a dielectric material of high thermal conductivity such asaluminum nitride (AlN), diamond like-carbon or an organosilicatedielectric also known as C-doped oxide (CDO) or organosilicate glass(OSG), such as SiCOH may be used as material of the second insulationlayer 31 to improve removal of excess heat from the semiconductorcomponent 1000. Furthermore, it is possible to better adapt the thermalexpansion coefficients of the semiconductor material and the material ofthe second insulation layer 31. Accordingly, thermal stress duringoperation of and/or soldering semiconductor component 1000 with its backside 102′ to a lead frame is reduced. For example, aluminum nitride maybe used as material of the second insulation layer 31 on a siliconsemiconductor body 100 to achieve both high thermal conductance and lowthermal stress at varying temperatures.

As already explained above with regard to FIGS. 1F and 1G, depositingthe second insulation layer 31 is typically performed at comparativelylow temperatures, like temperatures below 600° C. or even below 400° C.to protect structures already formed next to the first surface 101.Further suitable materials for low temperature forming of the secondinsulation layer 31 are boron-silicate glass, spin-on glass, silicone, apolymerized imide, a parylene or a polymerized benzocyclobutene, a curedresin, for example a cured epoxy resin such as SU8 or other syntheticmaterials. Of course, other standard dielectric materials ofsemiconductor technology such as silicon nitride may also be depositedas second insulation layer 31. Furthermore, the second insulation layer31 may be formed by galvanic oxidation.

According to an embodiment, the produced semiconductor component 1000includes a semiconductor body 100 with a first surface 101 and a backsurface 102′ opposite to the first surface 101, and at least oneinsulation trench 103 ₁, 103 ₂ formed in the semiconductor body 100. Afirst insulation layer 21 extends on at least one sidewall of the atleast one insulation trench 103 ₁, 103 ₂ from the first surface 101 tothe back surface 102′. A second insulation layer 31 is deposited on theback surface 102′ and includes at least one of aluminum nitride, diamondlike-carbon, boron-silicate glass, a spin-on glass, an organosilicatedielectric, a silicone, a polymerized imide, a parylene or a polymerizedbenzocyclobutene, and a cured resin or a another synthetic material. Thesecond insulating layer 31 may also be an oxide, for example formed byanodic oxidation. At least two semiconductor mesas 100 a, 100 b, 100 care formed in the semiconductor body 100 which are laterally insulatedfrom each other by the first insulation layer 21. At least one of thetwo semiconductor mesas 100 a, 100 b, 100 c is completely insulated onthe back surface 102′ by the second insulation layer 31. Accordingly, asemiconductor component 1000, typically an IC, with low leakage currentand low cross-talk between the semiconductor mesas 100 a, 100 b, and 100c is provided.

Typically, the at least one insulation trench 103 ₁, 103 ₂ issubstantially void-free. For example, the first insulation layer 21covers only the sidewalls of at least one insulation trench 103 ₁, 103 ₂and the residual trench is filled with a different dielectric materialor conductive material.

The semiconductor component 1000 typically forms an integrated circuitwith a plurality of semiconductor mesas 100 a, 100 b, 100 c which areinsulated from each other by the second insulation layer 31 and firstinsulation layers 21 arranged in respective insulation trenches 103 ₁,103 ₂ and at the sidewalls of the respective insulation trenches 103 ₁,103 ₂, respectively. Further examples are explained below with regard toFIGS. 30 to 33.

Referring to FIGS. 28 and 29, further embodiments for producingsemiconductor components are explained. After depositing the secondinsulation layer 31 on back surface 102′, as explained above with regardto FIG. 26, the second insulation layer 31 may be partially recessed toexpose at least one of the semiconductor mesas 100 a, 100 b, and 100 con the back surface 102′. The resulting semiconductor component 1002with exemplarily exposed semiconductor mesa 100 b is illustrated in FIG.28. Before or after formation of the second insulating layer 31, acontact or emitter implantation with e.g. P, As, Sb, B may be applied.

Thereafter, a metallization 56 may be formed on the back side 102′ inohmic contact with the exposed semiconductor mesa 100 b. Accordingly, abackside contact 56 is formed. The resulting semiconductor component1002 is illustrated in FIG. 29.

The backside contact 56 may, for example, form a drain electrode for aMOSFET-structure or a collector electrode for an IGBT-structure.Metallization 56 may be formed by deposition and may cover the backsurface 102′ completely. In other embodiments, metallization 56 isstructured so that different contacts are formed on the back side 102′.For example, a gate electrode and a drain electrode may be formed on theback side 102′ as explained above with regard to FIG. 9. When theinsulation trench 103 ₂ is filled with a conductive material 22, thisfilling may also be recessed on the back side 102′ and used as a throughcontact between a gate metallization arranged on back side 102′ and oneor more gate electrodes arranged next to the first surface 101.

A similar semiconductor component as illustrated in FIG. 29 may also byfabricated using SOI-technology. For example, deep vertical trenches maybe etched to a local buried oxide layer of a SOI-wafer and filled with adielectric material. However, this manufacturing method is moreexpensive due to the comparatively high prices of SOI-wafer.

Referring to FIG. 30, a further semiconductor component 2000 that may beproduced with the methods explained herein is explained. Semiconductorcomponent 2000 is similar to semiconductor component 1002 and alsoincludes two insulation trenches 103 ₁, 103 ₂ and a second insulationlayer 31 which is arranged on back surface 102′ and partially recessed.The insulation trenches 103 ₁, 103 ₂ and the second insulation layer 31form an insulating structure which insulates semiconductor mesas 100 a,100 b, 100 c from each other. However, the vertical cross-sectionthrough the semiconductor body 100 of semiconductor component 2000 ismore detailed.

Due to the insulating structure, three different circuits which areelectrically decoupled are formed in respective parts 200 a, 200 b, 200c and semiconductor mesas 100 a, 100 b, 100 c, respectively, ofsemiconductor component 2000. In the exemplary embodiment, only thesemiconductor mesa 100 c is in ohmic contact with back-sidemetallization 56 forming a metallization of a power n-MOSFET formed inpart 200 c. Back-side metallization 56 may be made of copper (Cu) whichis in contact with a drain region 54 formed by a lower portion 1 c ofsemiconductor mesa 100 c via an optional contact and barrier layer 54made of, for example, aluminum, titanium or silver. Several gateelectrodes 61 and field plates 63 are arranged in vertical trenchesextending from the first surface 101 into semiconductor mesa 100 c. Thegate electrodes 61 and field plates 63 are insulated from an n-typedrift region 2 c, a p-type body region 3 c and n ⁺-type source regions51 by a gate and field dielectric 62. On the first surface 101 aninterlayer dielectric 8 is arranged with through contacts 12 cconnecting source and body regions 51, 3 c to a source electrode 55 c orsource terminal 55 c formed by a source metallization 55 c on interlayerdielectric 8. Source metallization 55 c may also be made of copper andmay be covered with a protective layer 11 c of, for example NiP. Forsake of clarity, a gate metallization of the MOSFET is not shown in FIG.30.

Typically, semiconductor component 2000 forms an IC which includesfurther circuits in the parts 200 a and 200 b. These circuits may bepower circuits or logical circuits or measuring circuits which areconnected to respective metallizations 55 a (with optional protectivelayer 11 a) and 55 b (with optional protective layer 11 b) by throughcontacts 10 a, 10 b. The exemplary semiconductor zones 4 a and 4 b maybe of n-type and the exemplary semiconductor zones 3 a and 3 b may be ofp-type. However, the doping relations may also be reversed. Furthermore,the detailed structure of semiconductor mesas 100 a, 100 b typicallydepends on the desired functions of the IC. To facilitate front sidecontacting of the IC, the metallizations 55 a, 55 b and 55 c aretypically separated from each other and a further gate metallization(not shown in FIG. 30) by an insulating layer 17, for example anIMID-layer.

Referring to FIG. 31, a further semiconductor component 3000 that may beproduced with the methods explained herein is explained. Semiconductorcomponent 3000 is similar to semiconductor component 1002 but includes,in the shown vertical cross-section, three insulation trenches 103 ₁,103 ₂, 103 ₃. A second insulation layer 31 is arranged on back surface102′ and partially recessed. The insulation trenches 103 ₁, 103 ₂, 103 ₃and the second insulation layer 31 form an insulating structure whichinsulates semiconductor mesas 100 a, 100 b, 100 c from each other.

For sake of clarity only a right portion of an active area ofsemiconductor component 3000 is illustrated in FIG. 31. In the exemplaryembodiment, semiconductor device 3000 may be operated as a TEDFET(Trench Extended Drain Field-Effect Transistor). Accordingly,semiconductor body 100 includes a vertical MOSFET-structure insemiconductor mesa 100 a. For sake of clarity only a most right portionof the vertical MOSFET-structure is illustrated in FIG. 31. A gateelectrode 61 a which is insulated from adjacent semiconductor regions 2a, 3 a by a gate dielectric region 62 a extends from the first surface101 through the p-type body region 3 a and partially into an n⁻-typedrift region 2 a which forms a pn-junction 14 a with body region 3 a.N⁺-type source region 51 and p+-type body contact region (not shown inFIG. 31) are embedded in body region 3 a and in ohmic contact with asource metallization symbolized by the numeral S. The drift region 2 ais in ohmic contact with a drain metallization 56 via a drain contactregion 1 a. Drain contact region 1 a is typically formed from the backsurface 102′ after thinning semiconductor body 100, for example byimplantation and a subsequent drive-in process or anneal process. Inanother embodiment, optional n⁺-type semiconductor regions 1 b, 1 c arealso arranged in semiconductor mesa 100 b and semiconductor mesa 100 c,respectively, as indicate by the dashed-dotted line in FIG. 31. Themanufacturing of such a semiconductor component may even be simpler asno additional implantation process at the back surface 102′ arerequired, for example when the initially provided semiconductor body 100includes an n⁺-type semiconductor substrate and an n-type epitaxiallayer arranged thereon, as explained with regard to FIG. 19.

In addition, a drift channel control structure is formed insemiconductor mesa 100 b next to the MOSFET-structure formed inneighboring semiconductor mesa 100 a. A drift control region 2 b, whichmay also be of n⁻-type or p⁻-type, is arranged adjacent to drift region2 a. Drift control region 2 b is dielectrically insulated from driftregion 2 a by the first insulation layer 21 arranged in insulationtrench 103 ₁ and extending to the second insulation layer 31.Accordingly, drift control region 2 b is also insulated from drainmetallization 56. The function of the drift control region 2 b is tocontrol a conducting channel in the drift region 2 a along the firstinsulation layer 21 of insulation trench 103 ₁ if the MOSFET-structureis in its on-state. Drift control region 2 b therefore serves to reducethe on-resistance of the overall transistor component.

Unlike in usual MOSFETs, drift region 2 a of semiconductor component3000 may, disregarding of the type of the MOS transistor structure, ben-doped or p-doped. If, for example, in an n-type MOSFET-structure driftregion 2 a is n-doped, then an accumulation channel is formed along thefirst insulation layer 21 of insulation trench 103 ₁ and controlled bydrift control region 2 b. In this embodiment, the first insulation layer21 of insulation trench 103 ₁ is also referred to as accumulation layerand accumulation oxide, respectively. If drift region 2 a is p-doped inan n-type MOSFET-structure, then an inversion channel forms along thefirst insulation layer 21 of insulation trench 103 ₁ in drift region 2a, if the component is in its on-state. Like a usual MOSFET thiscomponent is in its on-state if a voltage is applied between a sourceregion 51 and a drain region 54 formed by a lower portion 1 a ofsemiconductor mesa 100 a and between source and drain metallizations S,56, respectively, and if a suitable electrical potential is applied togate electrode 61 a that effects a conducting channel in body region 3 abetween source region 51 and drift region 2 a. In an n-typeMOSFET-structure the voltage to be applied between drain region 54 andsource region 51 in order to switch the component in its on-state is apositive voltage, and the gate potential is a positive potential ascompared to source potential.

If the semiconductor component 3000 is in its on-state charge carriersare required in the drift control region 2 b to form the accumulation orinversion channel along the first insulation layer 21 of insulationtrench 103 ₁ in the drift region 2 a. In a semiconductor component 3000having an n-type MOSFET structure, holes are required in the driftcontrol region 2 b for forming this conducting channel. These chargecarriers in the drift control region 2 b are only required, if thecomponent is in its on-state. If the component is in its blocking mode,these charge carriers are removed from drift control region 2 band—equivalently to drift region 2 a—a space charge zone or depletionzone forms in drift control region 2 b. In this connection it should bementioned that drift control region 2 b may be of the same conductiontype as drift region 2 a or may be of a complementary conduction type.

The charge carriers that are moved from drift control region 2 b, if thecomponent is in its blocking mode or switched-off, are stored in anintegrated capacitor structure until the component is switched on forthe next time. This integrated capacitor structure is formed in aconnection region 3 b that adjoins drift control region 2 b and that isp-doped for an n-type component. Further, the integrated capacitorstructure can partly extend into drift control region 2 b. Connectionregion 3 b and drift control region 2 b act as the carrier layer for aninsulated electrode 61 b of the integrated capacitor structure.Electrode 61 b is insulated by a dielectric layer 62 b and in thefollowing also referred to as insulated capacitor electrode. Forproviding charge carriers to the drift control zone 2 b, if thecomponent is switched on for the first time, i.e., if the integratedcapacitor structure has not been charged, yet, drift control region 2 bmay be coupled to a gate terminal and gate metallization G,respectively, via a connection region 3 b. In this case, charge carriersare provided from a gate driver circuit (not shown in FIG. 31) that, inoperation of semiconductor component 400, is coupled to the gateterminal G. A diode 65 is formed between a p-type semiconductor zone 3 cand an n-type semiconductor zone 4 c in semiconductor mesa 100 c whichis insulated by the first insulation layer 21 of insulation trench 103 ₂and the second insulation layer 31. Diode 65 is coupled between gateterminal G and the connection region 3 b and serves to preventdischarging the drift control region 2 b in the direction of the gateterminal G. Due to insulating semiconductor mesa 100 b by an insulationstructure formed by first insulation layer 21 of insulation trenches 103₁, 103 ₂ and the second insulation layer 31, discharging drift controlregion 2 b to adjacent semiconductor regions 1 a, 2 a, and 2 c isprevented. In the exemplary embodiment, two different circuits, namely aTEDTFET and the diode 65, which are electrically decoupled by a wiringon the first surface 101, are formed in respective parts 300 a, 300 c ofsemiconductor component 3000 forming an integrated circuit. In furtherembodiments, the gate driver circuit and further circuits may also beintegrated, typically be formed in further insulated semiconductormesas. An example is explained with regard to FIG. 32.

Semiconductor component 3002 illustrated in the vertical cross-sectionof FIG. 32 is similar to semiconductor component 3000 and may also beformed with the methods explained herein. However, semiconductorcomponent 3000 further includes a circuit for charging the accumulationoxide 21 formed in insulation trench 103 ₁. In the exemplary embodiment,the circuit for charging the drift control region 2 b is formed ininsulated semiconductor mesa 100 d which is insulated from the othersemiconductor mesa 100 a, 100 b, 100 c at least by the first insulationlayer 21 of insulation trenches 103 ₃, 103 ₄ and by the adjoining secondinsulation layer 31. The circuit for charging the accumulation oxideincludes an electrode 61 d which is insulated by a dielectric region 62d. The electrode 61 d as well as a p⁺-type semiconductor zone 5 d anadjoining an n⁺-type semiconductor zone 55 d are connected with thedrain metallization as indicated by the reference sign D. A diode 67 isformed between a p-type semiconductor region 3 d, which adjoins thesemiconductor zones 5 d and 55 d, and an n-type semiconductor region 2d. As indicated by the reference sign DCR, an n⁺-type semiconductor zone6 d which adjoins the n-type semiconductor region 2 d is connected withthe drift control region 2 b that may be charged by the circuit forcharging the accumulation oxide via a not illustrated wiring.

Insulated semiconductor mesa 100 c includes a Z-diode 66 which isconnected between a charge gate terminal CHG and source terminal S, Notethat the exemplary circuitry illustrated in FIG. 32 typically includesfurther circuits and components, respectively, which are arranged infurther insulated semiconductor mesas. For example, a further diode 65as illustrated in FIG. 31 is typically also integrated and connectedbetween a gate terminal G and charge gate terminal CHG. Furthermore, atemperature measuring circuit and/or a current measuring circuit mayadditionally be formed in respective insulated semiconductor mesas.Accordingly, a complex IC with low cross-talk and/or low leakage currentmay be provided.

Referring to FIG. 33 showing a vertical cross-section through asemiconductor body 100, a further semiconductor component 3004 isexplained. Semiconductor component 3002 is similar to the semiconductorcomponent 3000, 3002 and may also be formed with the methods explainedherein. For sake of clarity, only a most right section of semiconductorcomponent 3004 is shown in FIG. 33. Since the drift control region 2 bis electrically insulated from the drain region (not shown in FIG. 33)and at back surface 102′, there is the risk of charge carriersaccumulating in the drift control region 2 b. In the case of an n-dopeddrift control region 2 b, when the component is in blocking mode,electrons and holes can be generated on account of thermal chargecarrier generation within the drift control region 2 b, the holes beingconducted away via connection region 3 b, while the electrons remain inthe drift control region 2 b and may negatively charge the drift controlzone 21 in the long term.

In order to prevent such charging of the drift control region 2 b, thedrift control region 2 b can be connected to the drain metallization 56via a rectifier element 69, such as a diode, for example, in the edgeregion 104 of the semiconductor body 100. In the exemplary embodiment,edge region 104 is formed in the laterally insulated semiconductor mesa100 f arranged between insulation trenches 103 ₂, 103 ₃. Similar asexplained above with regard to FIG. 31 for the diode 65, rectifierelement 69 may also be formed within semiconductor mesa 100 f as diode69.

Typically, a multiplicity of lattice defects is present along the edge13, the defects bringing about a sufficient conductivity of thesemiconductor body along the edge 13. The lattice defects result fromthe division, for example sawing apart, of a wafer into the individualsemiconductor bodies. Due to the first insulating layer 21 of insulationtrench 103 ₃, further drifting of lattice defects into an active area isavoided and thus the reliability of semiconductor component 3004increased.

Close to the first surface 101, the edge region 104 of semiconductorbody 100 is typically at the same electrical potential as the back side,for example on drain potential. When the semiconductor component 3004 isin blocking mode, the connection region 3 b is at an electricalpotential that is significantly lower than the drain potential. When thecomponent is in blocking mode, the edge region 104 is thus at drainpotential, while the connection region 3 b is at a significantly lowerpotential. Via the rectifier element 69, a connection zone 4 b isapproximately at drain potential when the component is in blocking mode.On account of the potential difference between the connection region 3 band the connection zone 4 b when the component is in blocking mode, aspace charge region forms in the drift control region 2 b in a lateraldirection as schematically illustrated by the dashed line 25. The spacecharge region takes up the voltage difference. In order to influence theelectric field, field plates 10 can be provided, of which one isconnected to the connection zone 4 b of semiconductor mesa 100 b and oneis connected to the connection zone 6 f of semiconductor mesa 100 f viadiode 69.

The optional semiconductor region 1 b doped more highly than the driftcontrol region 2 b ensures that the drift control region 2 b is, at itsdrain-side end, i.e. close to back surface 102′, at an identicalelectrical potential at all points.

It should be pointed out that instead of the edge termination with fieldplates 10 other edge terminations known in principle are also possiblee.g., on the basis of field rings, partially or fully depletable dopings(VLD edges, variation of lateral doping), coverings with insulating,semi-insulating or electroactive layers also in combination or incombination with field plates 10.

The rectifier element 69 can be realized as a diode, and may not have aparticularly high voltage blocking capability in the reverse directionbut rather prevent at least the flowing over of accumulation charge fromthe drift Io control zone 21 in a direction of the drain. However, inorder to prevent the charge carriers accumulated in the drift controlzone 2 b, that is to say holes in the case of an n-doped component, fromflowing away via the rectifier element 69 with the component driven inthe on state, the connection zone 4 b can be doped very highly.

Typically, the rectifier element 69 is also integrated in thesemiconductor body 100 similar as explained with regard to FIG. 31 forthe diode 65. Furthermore, the edge termination structure and the edgeregion 104 of semiconductor component 3004 may also be integrated intothe semiconductor component 3000 and 3002 explained above with regard toFIGS. 31 and 32, respectively. The resulting semiconductor componentsmay also be produced with the methods described herein.

The methods for producing semiconductor components as explained hereinhave the following processes in common: a semiconductor body with afirst surface and a second surface opposite to the first surface isprovided; at least one insulation trench which extends into thesemiconductor body from the first surface is formed; a first insulationlayer is formed on one or more sidewalls of the at least one insulationtrench; semiconductor material of the semiconductor body is removed fromthe second surface and a second insulation layer which extends to thefirst insulation layer is formed at the surface formed by removing thesemiconductor material from the second surface. Typically, that at leasttwo semiconductor mesas are formed which are insulated from each otherby the first insulation layer and the second insulation layer.

According to an embodiment of a method for producing a semiconductorcomponent, the method includes: a semiconductor body with a firstsurface and a second surface opposite to the first surface is provided;an insulation trench which extends into the semiconductor body from thefirst surface is formed; a first insulation layer is formed on one ormore sidewalls of the insulation trench; semiconductor material of thesemiconductor body is removed from the second surface to expose at leastparts of the first insulation layer, or to remove at least parts of thefirst insulation layer; and a second insulation layer which extends tothe first insulation layer is formed on the second surface.

Typically, at least two insulation trenches are formed in a verticalcross-section that is substantially orthogonal to the first surface toseparate semiconductor mesas from each other.

Alternatively, the two insulation trenches or 2 sections of oneinsulation trench are formed by etching a wide trench, covering thesidewalls of the wide trench by an insulator, removing the insulatorfrom the bottom of the trench and filling the empty space withmonocrystalline semiconductor material, typically by selective epitaxy.

According to an embodiment of a method for producing a semiconductorcomponent, the method includes: providing a semiconductor body with afirst surface and a second surface opposite the first surface; formingan insulation trench which extends into the semiconductor body from thefirst surface and which in a horizontal plane of the semiconductor bodyde-fines a via region of the semiconductor body; forming a firstinsulation layer at least on one or more sidewalls of the insulationtrench; removing semiconductor material of the semiconductor body fromthe second surface to expose at least parts of the first insulationlayer, to remove at least parts of the first insulation layer, or toleave at least partially a semiconductor layer with a thickness of lessthan 1 μm between the first insulation layer and the second surface;forming a first contact electrode on the via region in the region of thefirst surface; and forming a second contact electrode on the via regionin the region of the second surface.

According to an embodiment, the method further includes forming a secondinsulation layer on the second surface which extends to the firstinsulation layer.

According to an embodiment, the insulation trench is formed as a closedloop.

Typically, the via region is enclosed by the insulation trench. Further,the via region may be arranged outside the semiconductor region enclosedby the insulation trench.

According to an embodiment, the insulation trench together with an edgeof the semiconductor body or a scribe line disposed on the semiconductorbody forms a closed loop.

According to another embodiment, the semiconductor material is removedfrom the second surface so that the first insulation layer is uncovered.

According to an embodiment, the method further includes forming a firstinsulation trench which forms a first closed loop, and forming a secondinsulation trench which forms a second closed loop within the firstclosed loop, wherein the via region is arranged between the firstinsulation trench and the second insulation trench.

According to an embodiment, the method further includes introducingdopant atoms into the via region. The dopant atoms may, for example, beintroduced via the insulation trench and/or the first surface.

According to an embodiment, the method further includes completelyfilling the insulation trench with the first insulation layer.

According to an embodiment, the method further includes forming thefirst insulation layer on the sidewalls of the insulation trench so thata residual trench remains, and filling the residual trench with afilling material. The filling material may be an electrically conductivematerial.

According to an embodiment, the method further includes forming a dopedcontact region in the via region below the first surface, and producingthe first contact electrode such that it contacts the doped contactregion.

According to an embodiment, the method further includes producing aninsulation on the insulation trench on the second surface afteruncovering the first insulation layer.

According to an embodiment, the method further includes producing acontact trench in the via region, at least partially filling the contacttrench with an electrically conductive material; uncovering theconductive material at the second surface, and producing the secondcontact electrode so that the second contact electrode contacts theconductive material. Typically, the conductive material is a metal or adoped polycrystalline semiconductor material.

According to an embodiment, the insulation trench and the contact trenchare produced using one or more common method steps.

According to an embodiment, the method further includes producing a gateelectrode electrically connected to the first contact electrode in theregion of the first surface, producing a source region below the firstsurface and a source electrode electrically connected to the sourceregion and electrically insulated from the gate electrode at leastpartially above the first surface, and producing a drain electrodeelectrically insulated from the second contact electrode on the secondsurface, so that a MOS transistor is formed.

According to an embodiment, the method further includes providing thesemiconductor body with a first semiconductor layer and a secondsemiconductor layer on top of the first semiconductor layer, wherein thefirst semiconductor layer defines the second surface, and the secondsemiconductor layer defines the first surface, and wherein the sourceregion is formed in the second semiconductor layer.

According to an embodiment of a semiconductor component, the componentincludes: a semiconductor body with a first surface and a secondsurface; a first contact electrode in a region of the first surface; asecond contact electrode in a region of the second surface; asemiconductor via region extending between the first and second contactelectrodes; and an insulation layer separating the via region in ahorizontal direction of the semiconductor body from other regions of thesemiconductor body.

According to an embodiment, the semiconductor component is implementedas an MOS transistor, further including a gate electrode electricallyconnected to the first contact electrode in the region of the firstsurface, a source region arranged below the first surface, a sourceelectrode electrically connected to the source region, electricallyinsulated from the gate electrode, and arranged at least partially abovethe first surface, and a drain electrode electrically insulated from thesecond contact electrode on the second surface.

Although various exemplary embodiments of the invention have beendisclosed, it will be apparent to those skilled in the art that variouschanges and modifications can be made which will achieve some of theadvantages of the invention without departing from the spirit and scopeof the invention. It will be obvious to those reasonably skilled in theart that other components performing the same functions may be suitablysubstituted. It should be mentioned that features explained withreference to a specific figure may be combined with features of otherfigures, even in those cases in which this has not explicitly beenmentioned. Further, the methods of the invention may be achieved ineither all software implementations, using the appropriate processorinstructions, or in hybrid implementations that utilize a combination ofhardware logic and software logic to achieve the same results. Suchmodifications to the inventive concept are intended to be covered by theappended claims.

Spatially relative terms such as “under”, “below”, “lower”, “over”,“upper” and the like are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the device in additionto different orientations than those depicted in the figures. Further,terms such as “first”, “second”, and the like, are also used to describevarious elements, regions, sections, etc. and are also not intended tobe limiting. Like terms refer to like elements throughout thedescription.

As used herein, the terms “having”, “containing”, “including”,“comprising” and the like are open ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a”, “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

With the above range of variations and applications in mind, it shouldbe understood that the present invention is not limited by the foregoingdescription, nor is it limited by the accompanying drawings. Instead,the present invention is limited only by the following claims and theirlegal equivalents.

What is claimed is:
 1. A method for producing a semiconductor component,comprising: providing a semiconductor body with a first surface and asecond surface opposite to the first surface; forming an insulationtrench from the first surface into the semiconductor body so that theinsulation trench is, in a projection onto the first surface,substantially ring-shaped; forming a first insulation layer at least onone or more sidewalls of the insulation trench so that the firstinsulation layer forms, in the projection onto the first surface, afirst closed loop; removing semiconductor material of the semiconductorbody from the second surface to expose bottom portions of the firstinsulation layer and to form a back surface; depositing a secondinsulation layer on the back surface such that at least twosemiconductor mesas are formed which are insulated from each other bythe first insulation layer and the second insulation layer; forming acontact opening in the second insulation layer that extends to one ofthe at least two semiconductor mesas, such that the insulation trenchremains covered by the second insulation layer at the back surface afterthe contact opening is formed in the second insulation layer; forming anelectrode that contacts the one of the at least two semiconductor mesasat the second surface through the contact opening, the electrode beingseparated from the insulation trench by the second insulation layer; andforming a second insulation trench which forms, in the projection ontothe first surface, a second closed loop within the first closed loop. 2.The method of claim 1, wherein the second insulation layer comprises atleast one of a boron-silicate glass, a spin-on glass, a silicone, apolymerized imide, a parylene or a polymerized benzocyclobutene, anorganosilicate dielectric, a synthetic material, and a cured resin. 3.The method of claim 1, wherein the insulation trench is completelyfilled with the first insulation layer.
 4. The method of claim 1,further comprising filling the insulation trench with a conductivematerial prior to depositing the second insulation layer.
 5. The methodof claim 4, wherein the conductive material is selected from the groupconsisting of a doped amorphous semiconductor material, a dopedpolycrystalline semiconductor material, a metal, a silicide and carbon.6. The method of claim 1, wherein the second insulation layer ismask-less deposited on the back surface.
 7. The method of claim 1,wherein forming the insulation trench comprises a Bosch process.
 8. Themethod of claim 1, wherein the insulation trench forms a rectangularring or an ellipsoidal ring.
 9. The method of claim 1, wherein removingsemiconductor material of the semiconductor body comprises at least oneof grinding, polishing, a CMP-process and etching.
 10. The method ofclaim 1, wherein the semiconductor body is thinned to a verticalthickness between the first surface and the back surface of less thanabout 50 μm by removing semiconductor material of the semiconductorbody.
 11. The method of claim 1, wherein the semiconductor bodycomprises an epitaxial layer and wherein the insulation trench is etchedcompletely through the epitaxial layer.
 12. The method of claim 1,wherein the semiconductor body is thinned to a vertical thicknessbetween the first surface and the back surface by removing semiconductormaterial of the semiconductor body, wherein the insulation trench isetched to a vertical depth, and wherein the vertical thickness is about5% to 30% smaller than the vertical depth.
 13. The method of claim 1,further comprising mounting the semiconductor body with the firstsurface on a carrier system prior to removing semiconductor material ofthe semiconductor body.
 14. The method of claim 13, wherein mounting thesemiconductor body on the carrier system comprises attaching thesemiconductor body to a glass substrate.
 15. The method of claim 1,further comprising at least one of: forming a diode structure in atleast one of the at least two semiconductor mesas; forming a capacitancestructure in or on at least one of the at least two semiconductor mesas;forming a transistor structure in at least one of the at least twosemiconductor mesas; forming a gate electrode structure on the firstsurface and on at least one of the at least two semiconductor mesas;forming a trench gate electrode structure extending form the firstsurface into at least one of the at least two semiconductor mesas; and;forming on the first surface a wiring between the at least twosemiconductor mesas and/or to the diode structure and/or to thecapacitance structure and/or to the transistor structure and/or to thegate electrode structure and/or to the trench gate electrode structure.16. The method of claim 1, further comprising at least one of: partiallyremoving the second insulation layer to expose at least one of the atleast two semiconductor mesas on the back side; and, forming ametallization on the back side in ohmic contact with the at least one ofthe at least two semiconductor mesas.
 17. The method of claim 1, whereinthe second insulation layer is deposited at a temperature below 400° C.18. A method for producing a semiconductor component, comprising:providing a semiconductor body with a first surface and a second surfaceopposite to the first surface; etching an insulation trench from thefirst surface partially into the semiconductor body so that theinsulation trench surrounds, in a projection onto the first surface, asemiconductor region of the semiconductor body; forming a firstinsulation layer on one or more sidewalls of the insulation trench sothat the first insulation layer forms, in the projection onto the firstsurface, a first closed loop; filling the insulation trench with aconductive material; processing the second surface comprising at leastone of grinding, polishing, a CMP-process and etching to expose thefirst insulation layer; depositing on the processed second surface asecond insulation layer which extends to the first insulation layer;forming a contact opening in the second insulation layer that extends tothe processed second surface, such that the insulation trench remainscovered by the second insulation layer at the second surface after thecontact opening is formed in the second insulation layer; forming anelectrode that contacts the processed second surface through the contactopening, the electrode being separated from the insulation trench by thesecond insulation layer; and forming a second insulation trench whichforms, in the projection onto the first surface, a second closed loopwithin the first closed loop.
 19. The method of claim 18, wherein atleast two semiconductor mesas are formed in the semiconductor body whichare laterally insulated from each other by the first insulation layer.20. The method of claim 19, wherein at least one of the twosemiconductor mesas is completely insulated on the processed secondsurface by the second insulation layer after finishing processing thesemiconductor component.
 21. The method of claim 19, further comprisingprior to processing the second surface at least one of: forming anelectric component in or on at least one of the at least twosemiconductor mesas; and, forming on the first surface a wiring betweenthe at least two semiconductor mesas and/or to the electric component.22. The method of claim 18, further comprising finishing processing thesemiconductor component from the first surface prior to processing thesecond surface.
 23. The method of claim 18, further comprising prior toprocessing the second surface forming a TEDFET-structure in thesemiconductor body, wherein the first insulation layer forms anaccumulation oxide of the TEDFET-structure.
 24. A semiconductorcomponent, comprising: a semiconductor body with a first surface and aback surface opposite to the first surface; at least one insulationtrench formed in the semiconductor body, the at least one insulationtrench having, in a projection onto the first surface, a substantiallyring-shaped geometry and comprising a first insulation layer extendingfrom the first surface to the back surface and an electricallyconductive material extending from the first surface to the backsurface, the first insulation layer forming, in the projection onto thefirst surface, a first closed loop; a second insulation layer depositedon the back surface of the semiconductor body, the second insulationlayer covering the at least one insulation trench at the back surfaceand comprising at least one of aluminum nitride, diamond like-carbon, aboron-silicate glass, a spin-on glass, an organosilicate dielectric, asilicone, a polymerized imide, a parylene or a polymerizedbenzocyclobutene, a synthetic material, and a cured resin; at least twosemiconductor mesas formed in the semiconductor body, the at least twosemiconductor mesas being laterally insulated from each other by thefirst insulation layer, and at least one of the two semiconductor mesasbeing completely insulated on the back surface by the second insulationlayer; a contact opening in the second insulation layer that extends tothe back surface, such that the at least one insulation trench remainscovered by the second insulation layer at the back surface; an electrodethat contacts the back surface through the contact opening, theelectrode being separated from the at least one insulation trench by thesecond insulation layer; and a second insulation trench which forms, inthe projection onto the first surface, a second closed loop within thefirst closed loop.
 25. The semiconductor component of claim 24, whereinthe semiconductor component is a TEDFET, and wherein the firstinsulation layer of the at least one insulation trench forms anaccumulation oxide of the TEDFET.
 26. The semiconductor component ofclaim 24, comprising a plurality of semiconductor mesas which areinsulated from each other by respective insulation trenches and thesecond insulation layer.
 27. The semiconductor component of claim 24,wherein the at least one insulation trench is substantially void-free.28. The semiconductor component of claim 24, further comprising a gateelectrode structure at the first surface and at or in at least one ofthe at least two semiconductor mesas.